There has been rapid advancement in the field of electronic devices such as portable phones and portable information terminals in realizing smaller, thinner, and more lightweight devices. This progress has called for improvements in various components of these electronic devices, including a semiconductor device mounted in an electronic device, in terms of size, weight, function, performance, and packing density.
Currently, in some semiconductor devices, one approach to realize higher packing density and to reduce thickness and weight of the device is to mount a semiconductor element on a circuit board that is realized by forming an interconnection pattern on a thin insulating tape.
Examples of such semiconductor devices include TCP (Tape Carrier Package) and COF. In COF, no opening is formed to mount a semiconductor element, but the semiconductor element is mounted by being bonded to a thin insulating tape. The thin insulating tape used in COF is bendable to accommodate different applications. An interconnection pattern is formed on a surface of the insulating tape to realize a flexible circuit board. The interconnection pattern is electrically connected to the projecting electrodes formed on the semiconductor element. The external connectors of the interconnection pattern are connected to external devices such as a liquid crystal panel and a printed board.
For insulation, a solder resist is applied in the fabrication process to exposed portions of the interconnection pattern, other than the portion connected to the semiconductor element and the portion where the external connectors are provided.
One fabrication process of COF currently available is the MBB (Micro Bump Bonding). Another process, which has come into use in the last years, is a resin encapsulation process using an NCP (Non-Conductive Paste) or an ACP (Anisotropic Conductive Paste). These techniques are effective for semiconductor devices requiring multiple pins, narrow pitch, and edge touch. In the resin encapsulation process, an insulating resin is interposed between the semiconductor element and the flexible circuit board, and the projecting electrodes of the semiconductor element and the interconnection pattern on the flexible circuit board are connected to each other and sealed with the resin.
Examples of COF fabrication processes using a conventional MBB technique are disclosed in Tokukouhei (Published Japanese Translation of PCT international Publication for Patent Application) 2-7180 (published on Feb. 15, 1990; “Publication 1” hereinafter), and Tokukouhei 7-77227 (published on Aug. 16, 1995; “Publication 2” hereinafter).
In the technique disclosed in Publication 1, as shown in FIG. 3(a), a solder resist 5 is first applied to cover an interconnection pattern 2 on a circuit board 20 that has been prepared by forming the interconnection pattern 2 on an insulating tape 1. Here, the solder resist 5 is not applied to portions of the interconnection pattern 2 (these portions will be referred to as “contacts 4”) to be bonded with the semiconductor element, or to portions of the interconnection pattern 2 where the connectors are provided.
Then, as shown in FIG. 3(b), an insulating resin 14 is applied on the contacts 4. In the next step, as shown in FIG. 3(c), projecting electrodes (bumps) 6 of the semiconductor element 3 are aligned with the contacts 4 of the interconnection pattern 2, and the semiconductor element 3 is pressed down in the direction of arrow A. The pressure exerted on the semiconductor element 3 pushes out the insulating resin 14 under the semiconductor element 3 in the direction of arrow B, so that the insulating resin 14 is in contact with the projecting electrodes 6 of the semiconductor element 3 and the contacts 4 of the interconnection pattern 2, while allowing electrical connections between the two. Further, by being pushed out, the insulating resin 14 protrudes from the semiconductor element 3 around the edges of the semiconductor element 3.
Then, as shown in FIG. 3(d), the insulating resin 14 is cured to anchor the semiconductor element 3 on the circuit board 20. The insulating resin 14 is usually a light curable resin or a thermosetting resin. Accordingly, the insulating resin 14 is cured by irradiation of light or application of heat, as indicated by arrow D.
The technique disclosed in Publication 2 is illustrated in FIG. 4(a) through FIG. 4(d). The fabrication process of Publication 2 is the same as that of Publication 1 up to the step where the projecting electrodes 6 of the semiconductor element 3 are aligned with the contacts 4 of the interconnection pattern 2 and pressure is applied on the semiconductor element 3. In the next step, however, the process of Publication 2 energizes a pulse heating tool to heat the semiconductor element 3, as indicated by arrow C in FIG. 4(d), with the pressure being exerted on the semiconductor element 3. The applied heat cures the insulating resin 14 and anchors the semiconductor element 3 on the circuit board 20, with the projecting electrodes 6 of the semiconductor element 3 being electrically connected to the contacts 4 of the interconnection pattern 2.
One drawback of the foregoing conventional techniques is the poor strength and poor reliability of resin sealing. Further, the foregoing publications are associated with fabrication problems caused by the insulating resin, when the insulating resin rises to the pressure applying tool or heat applying tool used to apply pressure or heat to the semiconductor element. Therefore, the foregoing prior art techniques do not qualify as a technique for resin sealing.
Specifically, Publications 1 and 2 both employ a technique in which the projecting electrodes 6 of the semiconductor element 3 are aligned with the contacts 4 of the interconnection pattern 2, and pressure is exerted on the semiconductor element 3 to push the insulating resin 14 sideways to the edges of the semiconductor element 3, as shown in FIG. 3(c) and FIG. 4(c).
Thus, a phenomenon known as “resin repelling,” as indicated by arrow E, is caused when the amount of insulating resin 14 applied is small. Namely, due to poor wettability of the insulating resin 14, the pressure exerted on the semiconductor element 3 cannot spread the insulating resin 14, with the result that the insulating resin 14 remains in the vicinity of the semiconductor element 3. This may lead to a problem that a portion of the interconnection pattern 2 around the semiconductor element 3 is exposed in an area surrounded by the solder resist 5. Another deficiency is that the resin fillet, which is formed along the side surfaces of the semiconductor element to anchor the semiconductor element 3, cannot have enough size, with the result that the strength and reliability of resin sealing become poor.
The problem of exposed pattern in the interconnection pattern 2 can be solved by allowing the insulating resin 14 to more easily migrate to the solder resist 5. This can be carried out by increasing the amount of insulating resin 14 applied. However, by “resin repelling” as indicated by arrow E, the insulating resin 14 rises along the side surfaces of the semiconductor element 3 in the direction of arrow F when the projecting electrodes 6 of the semiconductor element 3 are pressed against the contacts 4 of the interconnection pattern 2. This is problematic because the insulating resin 14 adheres to the pressure applying tool and/or heat applying tool used to apply pressure and/or heat to the semiconductor element 3.
The problem of “resin rise” as indicated by arrow F is even more problematic these days in light of the development of thinner semiconductor devices with a proportionally reduced thickness of the semiconductor elements.